This invention relates generally to phase shift keying (PSK) data signalling systems and specifically to a new demodulator for use in a binary phase shift keying (BPSK) signalling system.
In BPSK signalling systems, two 180.degree. displaced phases of the carrier are used to indicate a "0" and a "1", respectively. The BPSK signal is generated by applying a data waveform and a carrier to a balanced modulator, the output of which is a double sideband suppressed carrier signal. Demodulation requires a carrier at the receiver having a phase that is close to one phase of the incoming BPSK signal.
The circuit that generates the carrier from the BPSK signal is called a carrier synchronizer. One configuration of a carrier synchronizer, called a remodulator loop, is shown in FIG. 1. In FIG. 1, an input signal is demodulated by a demodulator 1 and the recovered baseband signal is supplied to a low pass filter to remove the higher frequencies generated by the demodulation process. The baseband signal is supplied to a bit detector (not shown) and applied to a balanced modulator 7. The input signal is passed through a delay line 8 and applied to balanced modulator 7. The delay line is necessary to compensate for the low pass filter delay of the baseband signal. The output of the balanced modulator is connected to a phase detector 6 in a phase locked loop (indicated by the dashed line box). The balanced modulator output contains a carrier component at the input frequency for the PLL (Phase Lock Loop) to lock on. The PLL includes a voltage controlled oscillator (VCO) 3, a 90.degree. phase shift circuit 4 and a low pass filter 5, all of conventional construction. Since the PLL locks at -90.degree. relative to its reference, the input from VCO 3 to phase detector 6 is shifted by 90.degree. to enable the VCO output signal to demodulator 1 to be in phase with one of the phases of the input signal.
The circuit of the present invention, while based on the remodulator concept, uses simple logic gates. The inventive circuit is readily integrated and does not require the balanced modulator and multipliers of the prior art resulting in a cost saving. The inventive circuit also uses a novel sampling technique to demodulate a BPSK signal.